1–18GHz Wideband RF Downconverter Module

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Description

1–18 GHz Wideband RF Downconverter Module — Product Description

The 1–18 GHz wideband RF downconverter module is a high-performance RF receive front-end (TR module) featuring a single-channel architecture with two software-selectable IF output modes. It provides fixed IF center frequencies of 1.2 GHz (950–1450 MHz, 500 MHz bandwidth) and 1.8 GHz (1300–2300 MHz, 1 GHz bandwidth).

The module delivers a flat gain of 50 dB ±1 dB, a noise figure ≤ 6 dB, SFDR ≥ 60 dBc, image rejection ≥ 60 dBc, and generated spurious ≤ -50 dBc, offering superior linearity compared to conventional RF front-end components.

It integrates independent 6-bit digital RF and IF attenuators with 0.5 dB step size (0–20 dB RF / 0–25 dB IF), dual Ethernet and RS-422 control interfaces, a switchable internal/external 100 MHz reference clock, and real-time operating-status monitoring. Housed in a compact 100 × 100 × 20 mm enclosure weighing ≤ 0.75 kg, the unit meets IP68 sealing, operates across -30 °C to +65 °C, and incorporates an anti-vibration mechanical design—making it an ideal core front-end for microwave test equipment and field RF signal acquisition.

Key Specifications

Parameter Specification
Operating Frequency 1–18 GHz
IF Output Mode 1 (Center Frequency) 1.2 GHz (950–1450 MHz)
IF Mode 1 · 3 dB Bandwidth 500 MHz
IF Mode 1 · Anti-Aliasing Rejection @ 650 MHz ≥ 60 dB
IF Mode 1 · Anti-Aliasing Rejection @ 1750 MHz ≥ 60 dB
IF Output Mode 2 (Center Frequency) 1.8 GHz
IF Mode 2 · 3 dB Bandwidth 1 GHz (1300–2300 MHz)
IF Mode 2 · Anti-Aliasing Rejection @ 1100 MHz ≥ 60 dB
IF Mode 2 · Anti-Aliasing Rejection @ 2500 MHz ≥ 60 dB
RF-to-IF Gain (RF Att = 0 dB, IF Att = 0 dB) 50 dB ±1 dB
Output P1dB +25 dBm ±1 dB
Input 1 dB Compression Point (LNA) ≥ -15 dBm
RF Gain Flatness ±2 dB
Digital RF Attenuation (6-bit, 0.5 dB step) 0–20 dB
Digital IF Attenuation (6-bit, 0.5 dB step) 0–25 dB
SFDR ≥ 60 dBc
IF Output Filter Flatness ±1.5 dB
Frequency Lock Time ≤ 250 µs
Input Reference Clock 100 MHz
Input Reference Clock Power ≥ 0 dBm
Internal Reference Phase Noise @ 1 kHz < -150 dBc/Hz
Output Reference Clock 100 MHz
Output Reference Clock Power ≥ 5 dBm
Frequency Step 1 MHz
Noise Figure ≤ 6 dB
Generated Spurious ≤ -50 dBc
Phase Noise @10 kHz: < -80 dBc/Hz
@100 kHz: < -85 dBc/Hz
@1 MHz: < -100 dBc/Hz
Frequency Accuracy ±1 ppm
Frequency Stability ±1 ppm
Input Power Survivability ≥ +18 dBm
Image Rejection ≥ 60 dBc
Operating Voltage 12–14 V
Operating Current ≤ 3 A

 

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